1. Field of the Invention
The present invention relates to a semiconductor capacitive element, and more particularly, it relates to a method of manufacturing a semiconductor capacitive element, which can improve the quality of a dielectric thin film.
2. Description of the Background Art
One of passive elements forming a semiconductor integrated circuit device is a semiconductor capacitive element (capacitor). Such a capacitor is a basic and important element for forming a circuit. In general, a capacitor is formed by a dielectric film and a pair of electrode layers provided on both sides of the dielectric film. Voltage is applied across the electrode layers, thereby to store charges in the capacitor. The amount of charges storable in the capacitor, i.e., the so-called capacitance is in proportion to opposed areas of the electrodes and dielectric film, and in inverse proportion to the thickness of the dielectric film. In order to increase the capacitance, therefore, it is necessary to increase opposed areas of the electrodes and the dielectric film or reduce the thickness of the dielectric film.
On the other hand, technology development has been made to improve the density of integration of a semiconductor device, and a semiconductor element planarly formed on a semiconductor substrate is increasingly refined in structure. Under such circumstances, a plane occupied area of a capacitor, which is formed on a semiconductor substrate, is also reduced. In order to ensure prescribed capacitance on a reduced substrate surface, there has been invented a stacked type dynamic random access memory hereinafter referred to as D-RAM), in which a capacitor is stacked to be extended on a field oxide film and a gate electrode, as disclosed in Japanese Patent Publication Gazette No. 2784/1985 or 55258/1986, for example. In such a stacked type D-RAM, the capacitor is three-dimensionally extended to increase the junction area between electrodes, thereby to ensure capacitance. In another prior art example, a dielectric film is reduced in thickness independently of or in parallel with such a countermeasure in order to increase capacitance, as shown in "Reliability of Nano-Meter Thick Multi-Layer Dielectric Films on Polycrystalline Silicon" by Y. Ohji et al., 25th Annual Proceeding of Reliability Physics, pp. 55-59, 1987, for example. Such technique is now described.
FIGS. 8A to 8D show the structure of a capacitor having a lower electrode formed by a polycrystalline silicon layer along manufacturing steps. This capacitor is planarly stacked on the surface of a semiconductor substrate.
As shown in FIG. 8A, a silicon oxide film 2 is first formed on the surface of a silicon substrate 1. Then, a polycrystalline silicon film 3 of about 200 nm in thickness is deposited on the surface of the silicon oxide film 2 by thermal decomposition of silane (SiH.sub.4) gas through LPCVD (low pressure chemical vapor deposition). The deposited polycrystalline silicon film 3 is an aggregate of microcrystals of about 20 nm in crystal grain size. Thereafter an n-type impurity is added into the polycrystalline silicon film 3 by diffusion of phosphorus. The step of diffusing phosphorus is carried out by thermally diffusing phosphorus into the polycrystalline silicon film 3 from a source of POCl.sub.3 in a reaction chamber under a high temperature of 875.degree. C. The n-type impurity concentration of the polycrystalline silicon film 3 is set at to 10.sup.20 to 10.sup.21 /cm.sup.3 through the step of diffusing phosphorus. The above described step of introducing impurities to the polysilicon film 3 is not shown.
This phosphorus diffusion step is carried out under the temperature of 875.degree. C., which is considerably higher than the deposition temperature of the polycrystalline silicon film 3. Therefore, the polycrystalline silicon film 3 is so recrystallized that its crystal grain size is extremely increased to about 150 to 250 nm. Such recrystallization is promoted by the phosphorus added into the polycrystalline silicon film 3 in high concentration. The surface configuration of the polycrystalline silicon film 3 is extremely irregularized due to increase the grain size by such recrystallization. FIG. 9 is a sectional view showing crystal structure of the recrystallized polycrystalline silicon film 3.
Then, the recrystallized polycrystalline silicon film 3 is etched through photolithography and etching, to form a lower electrode pattern 3 as shown in FIG. 8B.
As shown in FIG. 8C, a silicon nitride film 4 of 7 to 10 nm in thickness is deposited on the surfaces of the silicon oxide film 2 and the lower electrode 3 by thermal reaction of dichlorosilane (SiH.sub.2 Cl.sub.2) and ammonia (NH.sub.3) through LPCVD. This silicon nitride film 4 forms a first layer in a dielectric film of the capacitor.
As shown in FIG. 8D, the surface of the silicon nitride film 4 is thermally oxidized to form a thin silicon oxide film 5 of 1 to 8 nm in thickness. This silicon oxide film 5 forms a second layer of the dielectric film. The thermal oxidation processing is performed in an atmosphere of wet O.sub.2 (oxygen containing water vapor) at 900.degree. C. The thin silicon oxide film 5 is adapted to improve dielectric breakdown voltage distribution and reliable lifetime of the capacitor. The reliable lifetime of the capacitor means the lifetime until more than a prescribed amount of leak current flows between both electrodes. Thereafter another polycrystalline silicon film 6 is formed on the surface of the silicon oxide film 5 through CVD. This polycrystalline silicon film 6 forms an upper electrode of the capacitor. The capacitor is formed through the aforementioned steps.
In the conventional capacitor whose capacitance is increased by reducing the thickness of the dielectric film, the silicon nitride film 4 forming the dielectric film is extremely reduced in thickness to 7 to 10 nm. However, the surface region of the lower electrode 3 on which the silicon nitride film 4 is formed is increased in crystal grain size due to recrystallization caused by high-temperature heat treatment for diffusing phosphorus. Thus, the surface region is extremely irregularized. Therefore, pinholes are easily formed in the thin silicon nitride film 4 through the rough surface of the lower electrode 3, while local electric field concentration is caused by such irregularity of the lower electrode surface to broaden the distribution of dielectric breakdown voltage among the capacitors, leading to reduction in reliable lifetime of the capacitor.
As described above, the conventional thin film capacitor has a drawback that the quality of the dielectric film is degraded and the reliable lifetime becomes shorter, since the grain size of the crystal is increased by the recrystallization of the lower electrode.